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Altera_Forum's avatar
Altera_Forum
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8 years ago

Cyclone IV/V Transceiver IO Standard | Biasing | Termination | PCIe

Hello, I have a fundamental question regarding the transceivers of Cyclone IV/V devices. The documentation says, that these transceivers support 'PCML-1.5V IO STANDARD' for TX lanes. https:...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

As you've stated - PCML is Pseudo CML. Altera can't call it CML because the construction of the I/O cell is not a true CML design. However, Altera's PCML ensures the behaviour of the I/O cell is appropriate for connection to a true CML device. It is a 'current-mode drive'.

I recommend you download the documentation and schematics for one of Altera's PCIe based development cards. This will clarify how they connect up an FPGA to a PCIe lane. You won't find any biasing resistors, only tx ac coupling caps.

Cheers,

Alex