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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cyclone IV using differential clock inputs with VCCIO at 3.3V

Hi all,

I'm considering using a Cyclone IV for a small project. The main requirement is that I have to input a differential clock to the FPGA. The differential clock has the LVDS or LVPECL standard.

I'm considering the DE0-Nano board because it has 2 pairs of DIFFCLK_p/n conveniently connected to expansion headers. I noticed all IO banks on the DE0-Nano board are powered at 3.3V. I also noticed VCCIO requirement for LVDS signals is 2.5V (not 3.3V).

My question is whether LVDS will work for clock inputs when VCCIO is 3.3V.

Thank you in advance

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    My question is whether LVDS will work for clock inputs when VCCIO is 3.3V.

    --- Quote End ---

    There's no specified differential I/O standard with 3.3V VCCIO. Plausibility considerations and experience tell, that it can work, at least with reduced performance. The achievable common mode range has to be evaluated.

    You'll need to specify a "fake" VCCIO of 2.5V for the respective bank.