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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cyclone IV using differential clock inputs with VCCIO at 3.3V

Hi all, I'm considering using a Cyclone IV for a small project. The main requirement is that I have to input a differential clock to the FPGA. The differential clock has the LVDS or LVPECL stan...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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My question is whether LVDS will work for clock inputs when VCCIO is 3.3V.

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There's no specified differential I/O standard with 3.3V VCCIO. Plausibility considerations and experience tell, that it can work, at least with reduced performance. The achievable common mode range has to be evaluated.

You'll need to specify a "fake" VCCIO of 2.5V for the respective bank.