Cyclone-IV turn Cyclone-II of Web Server.

Good night everybody.

Near , I tried together with the seniors ,

use Cyclone-II of design a new board .

And we with DE2-115 Internet(88E1111) turn to our board.

Then we reference the example code

"de2_115_web_server_rgmii_enet0" .

After , we creat new project (for Cyclone-II use)

In our project , have cpu、ram、sdram、flash、Enth Module、dma、timer.

(reference Attachments Internet Verilog.zip)

when we finish the SOPC Builder ,

we tree compiler , but QuartusII 11.0 tell me , my pll have question ↓

"error: mgl_internal_error: port object altpll|clk of width 5 is being assigned the port altpll|stratixii_pll inst pll1|clk of width 3 which is illegal, as port widths dont match nor are multiples. cause : the port widths are mismatched in the mentioned assignment. the port widths of the connected ports should match or the lhs port width should be a multiple of the rhs port width. action : check the port widths of the connected ports. logical operation results in a port width equal to the larger of the two ports and concatenation results in a port width equal to the sum of the individual port widths. double check for such cases."

I tree search this error of data , and tree change the SOPC Builder

of pll config , but still have same qusetion .

How do solve this it ... please give me someone advice.

P.S We Internet Oscillator is use Cyclone-II PLL of 25MHZ.

(PLL Output have : systme_clk、sdram_clk、enth_clk)