Cyclone IV SEU testing

Hi,

You may refer to https://www.intel.fr/content/dam/www/programmable/us/en/pdfs/literature/an/an357.pdf for more information on the timing.

In order to enable it you need to include the "cycloneiv_crcblock" on your FPGA design. If you only need to monitor the CRC Error then you can just enable it on your Quartus Project.