cyclone IV pcie ip core access host memory problem

Hi,

I have a design with pcie ip core on qsys , and i use a pc(linux 32bits) to be host .now i want to achieve to use the ip access the pc memory through the txs signals . i connect the txs slave to the bar0 master .

Frist , i allocate a 2k bytes host memory to the pcie bus address .

Second , i use bar to config the translation table .

Third , i write a data to the txs slave avalon address by bar master .

Then the question , if i write a 32bits data to 0x0 (base) or 0x2 or 0x4 , then can read a correct data by cpu and bar master , but i can't write a 32bits data to 0x1 or 0x3 or 0x5 correctly . If i write a 64bits data to 0x0(base) , the result is wrong .

Do anyone know the problem , tell me the maters .

thanks for help !