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Altera_Forum's avatar
Altera_Forum
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13 years ago

cyclone IV pcie ip core access host memory problem

Hi,

I have a design with pcie ip core on qsys , and i use a pc(linux 32bits) to be host .now i want to achieve to use the ip access the pc memory through the txs signals . i connect the txs slave to the bar0 master .

Frist , i allocate a 2k bytes host memory to the pcie bus address .

Second , i use bar to config the translation table .

Third , i write a data to the txs slave avalon address by bar master .

Then the question , if i write a 32bits data to 0x0 (base) or 0x2 or 0x4 , then can read a correct data by cpu and bar master , but i can't write a 32bits data to 0x1 or 0x3 or 0x5 correctly . If i write a 64bits data to 0x0(base) , the result is wrong .

Do anyone know the problem , tell me the maters .

thanks for help !

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    now i resolve this problem , a bug exists quartus 11.1 sp2 .Change to quartus 12.0 sp2 , everything's ok

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi

    I like to know how to access atom processor memory(DDR) from Nios II via PCIe interface?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I have to say sorry,

    I'm not familiar with Nios II , and now my projects are based on Xilinx device , so i can't give you a correct answer .

    If your project is based on Qsys system , you can refer to# 1 floor , there are three steps must be useful .
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi

    Thanks for your reply.

    Yes, my project is based on Qsys system.

    I have tried the above steps which you mentioned. From that I understand through "txs" we can access the host memory.

    So, I like to know is it "txs" of PCIe is accessing the DDR memory or some other internal memory?.(If you know how to see that, please help in it)

    If it is possible for you to share any reference design for the configuration we discussed.

    It will help me to access the host DDR memory.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    As i know, through "txs" we can access the memory, the memories are based on the pci-e address , if the momeries have no address , you can't read/write it ;

    About the reference design , i don't have any one now ,i'm sorry.