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mnasser431998's avatar
mnasser431998
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5 years ago

cyclone iv PCB design

Hello everyone, I am designing a custom board that hosts cyclone iv E BGA package. The board is intended to be used in video applications and SoCs therefore it has to have good amount of logic eleme...
mnasser431998's avatar
mnasser431998
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5 years ago

Thank you for your fast reply,

I have a further question related to IO. I noticed that DDR memories work SSTL IO standard which is about 1.2V and I know that I can change IO standard type in FPGA PinPlanner but how are these voltages are generated? do I need to generate them with external supply and connect the bank VCCIO to the supply I need to work with then change the IO standard type within the PinPlanner? or I can hook the VCCIO of all banks to a higher voltage for example 3.3V and then the FPGA internal circuitry takes care of generating the required voltage type? or there are specific voltages I need to connect the FPGA with( ex 3.3, 2.5, 1.2) in order to be able to generate all IO standards?

Thanks in advance

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    mnasser431998
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    5 years ago

    Thank you