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Gauthier_Auvray's avatar
Gauthier_Auvray
Icon for New Contributor rankNew Contributor
3 years ago

Cyclone IV GX ALTLVDS_RX

Hi, In a project we use ALTLVDS_RX (9 channels, de-serialization factor=6) in a Cyclone IV GX FPGA. If my understanding is correct: - SERDES is implemented in LE (with DDIO) - DPA is not available fo...
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello Gauthier,


Thank you for reaching out Intel FPGA Community.


I would like to recommend you check on this Knowledge Base article published regarding the error. You can refer to this link:

Warning (176441): The I/O pin < pin name > cannot meet the... (intel.com)


There is also community discussion that was similar on the error seen by you. Refer here:

Solved: Warning (176441): The I/O pin <name> cannot meet the timing constraints due to conflicting require - Intel Communities


I hope it helps you a bit.


Regards,

Aqid