Cyclone IV E Speed Grad and Design Issues

Hi,

For Altera Cyclone FPGAs they do not mention the fmax the core logic can operate at. The device speed grade is only an indication of the relative delay tpd of the device. As stated above, the higher the grade, the lower the performance. Thus a speed grade of -6 is faster than that of -8. The speed grade also determines the fmin and fmax of the PLLs and clock circuitry used in the FPGAs.

The fmax of any design implemented on FPGA is dependent on the architecture, critical paths and logic utilization of the design. For example, if your design uses a lot of LUTs and has a large combinational loop, then the fmax will be drastically affected and reduced. To get maximum performance of any digital design on FPGAs, you need to make sure combinational paths are minimum and flop are used more (FPGAs have more of Flops than combinational circuits). Making sure your critical path does not exceed the device speed grade ( for example 8ns for a C8 device) will ensure that you are able to meet the maximum possible performance of an FPGA.