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We have a test hardware with the DE0 NANO Board which has the FPGA EP4CE22F17C6. The target Fmax for our design is 50 MHz and it can be achived in the FPGA thats on the DE0 NANO board with a speed grade of 6. Now when we try to shift the design to EP4CEF17C8, where is 8 being lower in speed grade compared to 6, our restricted Fmax comes down to 40 MHz, for the same design and same setup.
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There is no surprise that you are getting lower Fmax if you migrated your design to higher speed grade C8 (means slower device).
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Can any one explain me the fundamental difference between the two speed grades
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Speed grade in older devices means actual delay thorough macrocell. In Cyclone family speed grade is relative performance of device. Higher speed grade means slower device (C8 is slower than C6). I think IC devices differ due to some variation in manufacturing process and after manufacturing IC is tested and slower devices are "thrown to one bin" (Higher speed grade for e.g. C8) and faster devices to "other bin" (Lower speed grade for e.g. C6).
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What surprises me is that from the altera website i have seen that C8 can go upto 400 Mhz and C6 upto 300 MHz. so for both of them 50 MHz would not be a problem i would guess
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Those numbers are in best case scenario and does not mean that you will achieve those numbers because it heavily depends from your design. For example if there is timing path between two registers and no combinational logic in between you might achieve specified performance in data-sheet but if you add long combinational path your design performance will suffer and you will no longer achieve specified performance.
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