Forum Discussion

ENava's avatar
ENava
Icon for New Contributor rankNew Contributor
2 years ago

Cyclone IV-E .sdc constraints for pin being both asynchronous and synchronous

Hi all! I need to interface a Cyclone IV-E to an AD9915 DDS synthesizer. AD9915 has a 32bit-wite parallel port that can be used both as: asynchronous address/data bus interface with read/write s...
Generic Io
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

I suggest setting the FPGA timing constraints based on the synchronous mode (using set_input/output_delay), and disregarding the set_false_path constraints used for the asynchronous mode. My reasoning is that data transfer during the asynchronous mode can be ignored. Therefore, setting the constraints for the synchronous mode would make more sense.


Regards,

Richard Tan