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YogeshaDG's avatar
YogeshaDG
Icon for New Contributor rankNew Contributor
5 days ago

Cyclone IV E – PLL Power Track Width Recommendation Clarification

Hi,

I am working on a design that uses the Cyclone IV E FPGA, and I’ve been following the Altera/Intel board design guidelines for PLL power routing. The document recommends using a minimum 20 mil trace width for the PLL power supply routing.

Due to space constraints on our PCB, we have routed the PLL supply net as follows:

  • From the ferrite bead to the FPGA cutout: 20 mil trace width
  • After the cutout region leading into the FPGA power pin area: reduced to 6 mil trace width

My questions are:

  1. Is it acceptable to reduce the PLL power trace width from 20 mil to 6 mil after the cutout region?
  2. If not, what issues might arise due to this narrower trace?

I have attached a snapshot from the guideline for reference.

Requesting your comments and guidance on whether this implementation is safe or if the narrower section could cause problems with PLL performance.

Thanks in advance!

Core Logic
Power

2 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    15 hours ago

    Hello, 

     

    6mil is normally for signal trace. Recommended power trace for PLL is 20mil, however it also depends on your how fast you want the PLL to run. 

    PLL power is only critical for high speed clock. The impact if the power delivery is not good to PLL during transmission, the clock signal will not clean, and maybe take longer time to lock. 

     

    regards,

    Farabi

    • YogeshaDG's avatar
      YogeshaDG
      Icon for New Contributor rankNew Contributor
      12 hours ago

      Hi, thanks for your response.

      In our design, the maximum clock frequency is 33 MHz, and the FPGA uses a 1 mm ball‑pitch package. Due to this, we are able to route the PLL net using a 20 mil trace width after the filtering section.

      From the filter output up to the FPGA cut‑out, the trace width remains at 20 mil.
      Inside the cut‑out, from the cut‑out region to the FPGA ball, the trace width is reduced to 6 mil to meet the package escape routing constraints.

      Regards,

      Yogesh