Cyclone IV assignment for 3xDDR2

Question

Hi,

I would like to assign the pins for 3 ddr2 components :

- fpga = EP4CE30 F484

- DDR2 micron 512mb x16 (MT47H32M16HR-25EG)

ddr1 = bank3 : dq3b x16 / dm3b x2 / dqs3b - dqs5b / clk - clkn=PLL1_CLKOUTp - PLL1_CLKOUTn

ddr2 = bank7 : dq5t x16 / dm3b x2 / dqs0t - dqs2t / clk - clkn=PLL2_CLKOUTp - PLL2_CLKOUTn

ddr3 = bank8 : dq3t x16 / dm3t x2 / dqs3t - dqs5t / clk - clkn=PLL3_CLKOUTp - PLL3_CLKOUTn

is it right ?

- 1 bank is not enought to assign all pins, can I choose any regular IO for other pins (addr, cas, ba, cs, odt, ras, we...) ? in any other banks ?

- there is only one couple rup/rdn per fpga side. does each couple can be use for the 2 banks ?

thanks

altera_forum · Answer

"AN 445: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces In Cyclone III Devices" table 7 gives me the answer for the pin assignment.

what does "altera recommends" means ? I don't have enough IO per bank to fit an entire ddr.

what are the consequences when cas, we, cke... are not in the same bank as dq and dqs ?

for rup and rdn i think like stratix devices, cyclone IV use 1 calibration circuit for 2 banks. but no clue for this point.

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