Cyclone IV assignment for 3xDDR2

"AN 445: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces In Cyclone III Devices" table 7 gives me the answer for the pin assignment.

what does "altera recommends" means ? I don't have enough IO per bank to fit an entire ddr.

what are the consequences when cas, we, cke... are not in the same bank as dq and dqs ?

for rup and rdn i think like stratix devices, cyclone IV use 1 calibration circuit for 2 banks. but no clue for this point.