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Altera_Forum
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13 years ago

Cyclone IV as transceiver using SMA

Hi all,

I am new on the world of the FPGA.

I have bought the Cyclone IV GX as i wanted to use it as transceiver.

I want to make a transmission through the SMA connectors, but i dont know how to make it. i have some doubts.

First, i dont know what kind of code i can implement in Quartus II

.I mean, if i create a code with PRBS data and another one for control de clocks, i can make the transmission??

or i need to implement as well some kind of protocol or something else?

i am a little bit lost, and i cant find that much info about this kind of transmission (signals, pins, etc).

Thanks in advance.

Lucia

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hi,

    Have you already written in VHDL or Verilog?

    You must visit several pages:

    At first http://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.html

    you will find some PDF like http://www.altera.com/literature/manual/rm_civgx_fpga_dev_board.pdf

    page 34, you can see the transceiver interface which you can use: PCIe, 10/100/1000 Ethernet

    --- Quote Start ---

    i am a little bit lost, and i cant find that much info about this kind of transmission (signals, pins, etc).

    --- Quote End ---

    For the pins, watch the schematic in the folder "kits" which you had to install. Don't forget that the standard for SMA is LVDS, you will need this information in the pin planner.

    --- Quote Start ---

    .I mean, if i create a code with PRBS data and another one for control de clocks, i can make the transmission??

    --- Quote End ---

    Which kind of transmission do you want to make? which flow rate do you want?
  • Altera_Forum's avatar
    Altera_Forum
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    thanks a lot for the answer Cs1400.

    The development kit i have bought is the Cyclone IV GX Transceiver Starter KIt, in which are embebed SMA connector for making transmission through them, being able of seeing the eye diagram later on in the osciloscope.

    http://www.altera.com/products/devkits/altera/kit-cyclone-iv-starter.html

    The problem i have is that i dont know how to make the code. If you see the page 2-22 of the manual is talking about the SMA connector, but is just saying some changes you need to make in the fpga for using them.

    i dont know if i need to use some protocol or just create a PRBS and a clock code.

    i have checked in the device handbook and i have found the pins in which the transmitter & the receiver are connected to

    ( SMA_TX_P -> ENETR_TX_P -> C2

    SMA_TX_N -> ENETR_TX_N -> C1

    SMA_RX_P -> ENETR_RX_P -> E2

    SMA_RX_N -> ENETR_RX_N -> E1 )

    but i also dont know how to use this signals.

    I want to make a variable rate transmission, which is going to depend on the lenght of the PRBS data. (but i want to start with a transmission of 2,5 Gbit/s)

    Thanks you so much.
  • Altera_Forum's avatar
    Altera_Forum
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    Don't write the code so fast if you begin!

    Do you use VHDL or Verilog?

    Do you know the exact FPGA name? (you will need it in Quartus)

    Read documentation about Cyclone IV GX and about tranceiver in FPGA Board.

    I know what you are doing: I use the Stratix V GX with a transceiver for Ethernet 10Gbps and I work with SMA. But I use another protocol, unavailable on Cyclone IV.

    You must design a system which manage the protocol. I advise you to use the IP of Altera, and to search some example. Which version of Quartus do you have?

    --- Quote Start ---

    (but i want to start with a transmission of 2,5 Gbit/s)

    --- Quote End ---

    PCIe Gen1 is what you need, according to this page http://www.altera.com/devices/fpga/cyclone-iv/transceivers/cyiv-transceivers.html
  • Altera_Forum's avatar
    Altera_Forum
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    Thanks, you are helping me a lot!

    I am using VHDL, and the name of the FPGA i am using is ECGX15BF14C8.

    I have made some easy programs for knowing the FPGA and Quartus II. ( I am using the version 12.0)

    I am actually reading the Cyclone IV handbook, but the thing i didnt know is that for making transmission with SMA connectors it was need a protocol, and i wasnt focus on reading about the PCIe protocol.

    The thing is that i cant make ethernet transmission, because in Cyclone IV when you enable the SMA conncetors, you disable the ethernet output as they are using the same tracks.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    I am actually reading the Cyclone IV handbook

    --- Quote End ---

    It is too long to read (488 pages!!!). Look for the transceiver and transceiver with Cyclone IV.

    --- Quote Start ---

    but the thing i didnt know is that for making transmission with SMA connectors it was need a protocol, and i wasnt focus on reading about the PCIe protocol.

    --- Quote End ---

    When you design a system of communication, you always need a protocol, you must manage the physical layer at least. Our transceivers manage PHY (physical layer) with sub-layers PMA and PCS.

    --- Quote Start ---

    The thing is that i cant make ethernet transmission, because in Cyclone IV when you enable the SMA conncetors, you disable the ethernet output as they are using the same tracks.

    --- Quote End ---

    Anyway, you only need the SMA. Be careful, Ethernet is the name for the interface AND the protocol! Even if you can't use Ethernet interface (RJ45 link), you can transmit and receive data encapsulated in the Ethernet protocol through the SMA.
  • Altera_Forum's avatar
    Altera_Forum
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    hi again,

    Ok, now i start to understand a bit how to make it , and how to implement the protocol...

    but know more doubts are showing up.

    i have made the implementation of the protocol with ALTGX, i have create my PRBS data and my FSM for controling the system. When i am trying to make it work i dont know where to connect some signals like tx_clkout, tx_dataout, or coreclockout.

    Also when i dont understand why for example pll_inclk is in format "std_logic_vector (0 downto 0).

    Thanks in advance
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    When i am trying to make it work i dont know where to connect some signals like tx_clkout, tx_dataout, or coreclockout.

    --- Quote End ---

    I can't help you because I worked with IP generated by MegaWizard (a tool of Quartus).

    --- Quote Start ---

    Also when i dont understand why for example pll_inclk is in format "std_logic_vector (0 downto 0).

    --- Quote End ---

    Altera uses a lot "std_logic_vector(N downto 0)" and N depends of something. In your case N=0, be careful: std_logic_vector(0 downto 0) is a different type of std_logic.

    Good luck