Forum Discussion
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- When i am trying to make it work i dont know where to connect some signals like tx_clkout, tx_dataout, or coreclockout. --- Quote End --- I can't help you because I worked with IP generated by MegaWizard (a tool of Quartus). --- Quote Start --- Also when i dont understand why for example pll_inclk is in format "std_logic_vector (0 downto 0). --- Quote End --- Altera uses a lot "std_logic_vector(N downto 0)" and N depends of something. In your case N=0, be careful: std_logic_vector(0 downto 0) is a different type of std_logic. Good luck