Forum Discussion
Altera_Forum
Honored Contributor
13 years agohi again,
Ok, now i start to understand a bit how to make it , and how to implement the protocol... but know more doubts are showing up. i have made the implementation of the protocol with ALTGX, i have create my PRBS data and my FSM for controling the system. When i am trying to make it work i dont know where to connect some signals like tx_clkout, tx_dataout, or coreclockout. Also when i dont understand why for example pll_inclk is in format "std_logic_vector (0 downto 0). Thanks in advance