Hallo Everybody, I would like you guys to suggest a solution for the problem below: I have successfully updated the hardware and software configurations of my project on the EPCS device and have tested the device by resetting it. Everything works perfectly. Now I did my experiments with the Nios II flash programmer. And there were no problems. now considering a situation where a connection through the jtag interface is not available, i would like to perform the update also through a fieldbus or ethernet. i have already read up on preparing the configuration files to be written to the flash (elf2flash, sof2flash). i can also transfer the files and store it in the flash memory. now my question is, if i am using the default epcs boot copier, do i write the fpga configuration first and then the software application, one after the other on to the flash?? or is there a specific rule, how i store these files on to the flash memory? If there are any other posts or documentation that I can read with respect to this issue, please let me know. Thank you very much Cheers kaushik.

Have you already read AN521 ? Moreover, if you search the forum for "remote update" you'll find a lot of threads on this subject. For example this one: http://www.alteraforum.com/forum/showthread.php?t=20623

Thank you very much for the reply. I have read the AN521 already and from your post I have read the related topics from other posts. I have achieved in successfully copying the required firmware files on to the Flash device. But now when I reset it it would not start. And I am guessing it has something to do with the Bootloader. I would like to first use the default bootloaders from Altera. the question is where should i specify which bootloader i would be using. should i be integrating the bootloader in to the sof or the elf file or should i copy it reperately to the epcs on-chip rom.

The bootloader is part of the EPCS controller integrated in the SOPC/QSys system. Just point the Nios CPU's reset vector to the EPCS controller and the bootloader will load the .elf file from the flash. The bootloader will jump over the .sof image, so the .elf just needs to be placed after the FPGA image in the flash. What file format are you using when you send data to your application, and how do you write it to the EPCS? The easiest format is probably .rbf, but IIRC with the EPCS flash you need to revert the bit order of every byte before you write them.

The bootloader is encapsulated in the fpga configuration, namely in the sof file. When you add a epcs controller, the default bootloader is automatically added to the project and built in fpga configuration. You should have a epcs_controller_boot_rom.hex in your Quartus project directory; if I recall correctly this is the default name associated to epcs, but you can change it in Quartus settings or in Qsys. If you need a custom bootloader you simply change the file and rebuild fpga. When you regenerate the Qsys component including epcs controller, the hex file is automatically overwritten with the default one. So you must pay attention to replace it with the custom version whenever you change anything in Qsys.

Thank you for the reply. Regarding my firmware files, here is how I prepare them: 1. I use the Nios II Command shell, to generate the hardware and software firmware files using sof2flash and elf2flash. 2. Then I comvert them in to the .bin files. 3. Finally I concatenate them. I am using ADS over EtherCAT protocol to transfer the files in segments to the device and then use the stand Altera flash access functions to write the file on to the flash starting from offset 0x00000000. So far this has not worked. What am i doing incorrectly here??

Cyclone IV and Nios II Firmware Update | Altera Community

24 Replies

Altera_Forum
Honored Contributor
14 years ago
I'm glad it works now! If it can be any comfort I didn't see it the first time I read your commands, it was only when I was re-reading my answer that I got the idea and read your message again ;)
Altera_Forum
Honored Contributor
14 years ago
Hallo,

Well I actually saw that error myself today morning and guess what, I changed the order and VOILA!! The update is working perfectly.. Well it was a very dumb mistake from my part, when from the start of this thread everybody has been saying something about the order of files. I must have seen it sooner. Anyway, this problem is now solved and this thread has been very educational.

I would like to thank everybody for your patience and your responses. Especially Daixiwen, for your timely replies.

Thanks.
Altera_Forum
Honored Contributor
14 years ago
No the Nios2 programmer just flashes the contents it reads from the given .flash file, it doesn't write anything else. My guess about the +15kB is that it zero fills the last flash page, but I can't be sure.

There are two things I see in your set of commands: first when you write this:
cat SoftwareFirmware.bin HardwareFirmware.bin > Firmware.bin
the software will be put in the flash before the hardware, and the FPGA will not boot. You need to put your two binary files in the other order. Second I'm not sure about the use of nios2-elf-objcopy to translate a srec file to binary. I've never used it that way and I don't know if it gives the expected results... Maybe you could try to use another tool (such as the very good srec_cat (http://srecord.sourceforge.net/)) to generate the binary file. srec_cat can also to the concatenation of the two .flash files, using the addresses to place the data correctly, so you are sure they it will always be put in the right order in your resulting binary file.
Altera_Forum
Honored Contributor
14 years ago
Ok.. Here is the thing. I used the flash file i am programming, and used the Nios2-flash-programmer to program my flash. It works great. See below the log.

bash-3.1$ nios2-flash-programmer --epcs --base=0x3001800 "c:/User/kaushik/WIDri
ve/flash/Firmware.flash" --program --erase-all --go
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Checksummed/read 896kB in 21.2s
Erased 7680kB in 95.1s (80.7kB/s)
Programmed 881KB +15KB in 6.8s (131.7KB/s)
Did not attempt to verify device contents
Starting processor at reset vector (0x03001800)

If you see the last but one line it says, programmed 881KB + 15kB. What is this 15 kB.. Is it more metadata required for the correct booting of the system??
Altera_Forum
Honored Contributor
14 years ago
I transfer the bin file to my device through ADS over EtherCAT protocol. I have checked at the receiving end if there is any dataloss but the data is intact. And then I use the alt_write_flash function to write the whole data in to my flash device with offset as '0' and length equal to the my file size.

Please find below the commands that I use to convert my flash files to a bin file. Are they alright??

sof2flash --input=widrive.sof --output=widrivehardware.flash --epcs --verbose

elf2flash --input=drive_fpga.elf --output=widrivesoftware.flash --epcs --after=widrivehardware.flash --verbose

nios2-elf-objcopy -i srec -o binary widrivesoftware.flash softwarefirmware.bin"

nios2-elf-objcopy -i srec -o binary widrivehardware.flash hardwarefirmware.bin"

cat softwarefirmware.bin hardwarefirmware.bin > firmware.bin
Altera_Forum
Honored Contributor
14 years ago
as far as I know the only thing the flash programmer does is convert the elf file to a srec file before flashing it. As long as your binary file has the same contents than this srec file it should work.
How do yo generate your binary file to flash?
Altera_Forum
Honored Contributor
14 years ago
Thanks Daixiwen for your answer..

I cannot still get the software to boot.. It got me thinking. I looked at the nios2-flash-programmer logs and the flash programmer actually adds a little more data to the nios2 firmware before it copies it into the location after the hardware firmware.

I mean, do I need to add something like address information, or pack the .bin file in to a Boot record before I flash it. If yes, then could you please give me a example??

Thanks a lot.
Altera_Forum
Honored Contributor
14 years ago
About your first question, the software should be written into the flash just after the FPGA image. AFAIK the bootloader isn't block aware, and will just get the FPGA image size from it header in the first few bytes, jump over it and start reading the elf image.
For your second question there isn't any significant difference in that area between the Cyclone III and IV so it should work. I have several projects here on Cyclone IV with the standard EPCS boot loader and they boot fine.
Altera_Forum
Honored Contributor
14 years ago
Hey Guys,

I have another question. The EPCS bootloader sources that i found in my NIOS installation folder, only contain files up to Cyclone III. I mean, the Cyclone III bootloader file is automatically added to my Quartus EPCS configuration, but I use a Cyclone IV device. Is this bootloader, basically compatible with the Cyclone IV device??

Thanks.
Altera_Forum
Honored Contributor
14 years ago
Here is another question:
I am writing the complete concatenated bin-file in to the flash with one single flash write function. That means that the hardware and the software firmwares are actually placed one after the another irrespective of the "Blocks" in the flash. Do I need to worry about this??

I mean, should I first write the hardware firmware and if it ends in the middle of a flash block, then start writing the software firmware in the next block??

I would like to thank all of you for your previous answers..

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Cyclone IV and Nios II Firmware Update

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