Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

CYCLONE III with AS and JTAG (SFL)

Hello everybody!!!

I'm creating a new schematic to my last project

I use a EP3C16Q240 with a serial configuration device (EPCS4) and i have a limited size to my board so i use just 1 jtag connector (Figure 9-30 device handbook cyclone III).

they are 2 case:

1/ i use JTAG to programm and debug the FPGA

2/ i use AS to programm EPCS throught the JTAG connector (with bridge into FPGA from JTGA to ASMI connection).

I have several doubts.

1/ We need to create serial flash loader megafunction to do the bridge. Where must i connect noe_in and must i share ASMI interface with my design?

2/ So to programm EPCS with SFL and AS , i had to programm before the CYLONE III with JTAG, is that it?

3/The PIN 4 of JTAG connector is at 2.5V(VCCA) and the pull-up on TCK and TDO are connected also at 2.5V(VCCA) or 3.3V(VCCIO of JTAG pins bank)? Must i connect the pin 6 of JTAG connector to VCCA also?

4/ And finally, Is it possible to replace a component EPCS4 equivalent such as m35p40?

Thank you in advance to your replies!!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    And enclosed the configuration schematic. Is it OK?

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I see one issue:

    p164

    http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf

    "Altera recommends connecting the MSEL pins to VCCA or GND"

    You have the pull-ups to VCCIO.

    Check whether you need pull-up/downs on the EPCS interface (I don't recall whether there are pull-ups on the FPGA or EPCS device, so just check).

    I don't see any decoupling capacitance, but assume that is on another page.

    I see you've protected the JTAG connector with TVSes, so thats good.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    yes, there was one issue, thanks!!! i changed the MSEL pull-ups to VCCA.

    Regarding the pull-ups on the EPCS interface, i looked the schematic on CYCLONE iii device handbook

    "Figure 9–30. Programming Serial Configuration Devices In-System Using the JTAG Interface" P217:

    and there are no pull-up or pull-down.

    I put of course a couple of decoupling capacitances.

    Just another question: To load a configuration into the EPCS4,

    - i have to load the configuration in the first time in the FPGA with JTAG connection and .SOF file (with a SFL megafunction

    and "noe_in" to "0")

    - Then i convert SOF file in .JIC file (JTAG indirect configuration) with quartus

    - I send this file with JTAG connection to the EPCS4 through CYCLONE iii (SFL bridge).

    Finally my FPGA can run and configure himself automatically at the power-up.

    Is-it exact?

    Thank for your reply.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Regarding the pull-ups on the EPCS interface, i looked the schematic on CYCLONE iii device handbook

    "Figure 9–30. Programming Serial Configuration Devices In-System Using the JTAG Interface" P217:

    and there are no pull-up or pull-down.

    --- Quote End ---

    Do not take figures in the handbook as an implementation recommendation, think of them more as a general guide. You need to read the data sheet for the EPCS device, and look in the handbook for comments regarding pull-ups on the configuration pins. You can also look at schematics of Altera evaluation boards. Keep in mind that a weak pull-up might be too weak, and that you should have an external pull-up. Its also easy to have an external pull-up on say chip-select and then not load it. Also check for signals that get tri-stated, eg., the data pins. You do not want those pins to float, so again, you need to see if there are weak pull-ups/downs or bus hold features on the devices, or whether you need external resistors.

    --- Quote Start ---

    Just another question: To load a configuration into the EPCS4,

    - i have to load the configuration in the first time in the FPGA with JTAG connection and .SOF file (with a SFL megafunction

    and "noe_in" to "0")

    --- Quote End ---

    You've mixed up your configuration schemes. The JTAG header does not need nCE in JTAG mode. You only need that pin on the header if the EPCS pins connect to both an AS header and to the FPGA. In that case you deassert nCE to tri-state the FPGA drivers. Your design uses JTAG mode only, so you do not need the nCE connection from the header. Connecting nCE to ground would be fine (though there is no problem using a resistor too).

    --- Quote Start ---

    - Then i convert SOF file in .JIC file (JTAG indirect configuration) with quartus

    - I send this file with JTAG connection to the EPCS4 through CYCLONE iii (SFL bridge).

    Finally my FPGA can run and configure himself automatically at the power-up.

    Is-it exact?

    --- Quote End ---

    Yes, that is correct. If I recall correctly, the DE0-nano user manual has a nice description of using SFL to program the EPCS device on that board.

    Cheers,

    Dave