CYCLONE III with AS and JTAG (SFL)

I see one issue:

p164

http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf

"Altera recommends connecting the MSEL pins to VCCA or GND"

You have the pull-ups to VCCIO.

Check whether you need pull-up/downs on the EPCS interface (I don't recall whether there are pull-ups on the FPGA or EPCS device, so just check).

I don't see any decoupling capacitance, but assume that is on another page.

I see you've protected the JTAG connector with TVSes, so thats good.

Cheers,

Dave