Cyclone III: Using PLL_CLKOUT (Clock Out) pin as general purpose IO?

I think, both questions are clearly answered in the device handbook respectively pinout tables.

The pinout table clarifies, that PLLx_CLKOUT is an optional function of particular regular IO pins. (The basic function is indicated in the column Pin Name/Function). So any of these pins can be used for regular IO, if not required as dedicated clock output.

Regarding pin capacitances, Table 1-9 in Cyclone III Device Handbook lists the standard and special pins capacitances. The said dedicated clock output pins are obviuosly belonging to the category I/O pin. This isn't surprizing because they are regular I/O pins. Their optional function doesn't involve changes to the I/O cell itself rather than input connectivity only.

Hi,

Why I asked this is because there is a fine print at the bottom of table 7-2 of C3 Handbook...it says "User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only" I think it is ONLY refering to differential I/O only...

There is no "dedicated clock output" in table 1-9 (C3 datasheet) but there is "delicated LVDS output". Are you referring to this? But PLLx_clock_output is located at bank 3 4 7 8, or top/bottom....and not left/right...

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I think, both questions are clearly answered in the device handbook respectively pinout tables.

The pinout table clarifies, that PLLx_CLKOUT is an optional function of particular regular IO pins. (The basic function is indicated in the column Pin Name/Function). So any of these pins can be used for regular IO, if not required as dedicated clock output.

Regarding pin capacitances, Table 1-9 in Cyclone III Device Handbook lists the standard and special pins capacitances. The said dedicated clock output pins are obviuosly belonging to the category I/O pin. This isn't surprizing because they are regular I/O pins. Their optional function doesn't involve changes to the I/O cell itself rather than input connectivity only.

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I think, it should be clear in my post, that I used "the said dedicated clock outputs" as another word for PLLx_CLKOUT. There are no other clock outputs available with Cyclone III.

As table 7-2 is dealing with differential I/O, the said note (1) is obviously referring to the availability of differential pairs among total I/O pins. Differential clkout pairs (or PLLx_OUTPUT, which is, as you should have learned now, the same for Cyclone family) can be used as regular I/O, but not as standard differential (=LVDS data) in- or output.