Cyclone III reset and configuration

Here are some answers to your extensive questions.

Please note these are only my two cents. I don't assure you this is the optimum: I simply state what I usually do and this has never created problems with CIII devices so far.

- JIC via SFL : this is a common practice. Nobody wants an extra connector. Time performance is not an issue because you need to flash the device once when the board is deployed.

- precautions against fpga damage : generally you only need to secure the i/o lines connected to outer world. Jtag is supposed to be used in a controlled environment and/or by competent personnel, so this is not critical. Anyway, for jtag lines I'd rather use 100ohm series resistor instead of the 47ohm+100pF to ground.

- 470pF capacitor or, worse, open circuit, would prevent proper device reset in case MAX823 nRESET output is initially or permanently asserted. I think you can simply disable the MAX823 reset feature by simply leaving WDI unconnected. Then, directly connect reset to nCONFIG and place a removable jumper on WDI

- I've never had problems with DCLK signal integrity. Usually EPCS is very near to FPGA, so this is not an issue. I always connected DCLK directly and never used a termination like yours.