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Altera_Forum's avatar
Altera_Forum
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15 years ago

Cyclone III PLL Lost Lock

Hi Everyone,

I have a problem here, I have a Cyclone III project utilizing a PLL. I set the PLL to generate 192 Mhz clock from input inclk0 50 Mhz (my board has this clock source). When I simulate my design in ModelSim, everything seem ok, but ModelSim give me somekind of warning message : 


#  ** Note: Cyclone III PLL locked to incoming clock
#     Time: 410 ns  Iteration: 3  Instance: /receiverfinal_vhd_vec_tst/i1/comp_sckg/comp_fpll/altpll_component/cycloneiii_altpll/m5
#  Simulation passed !
#  ** Note: Cyclone III PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.
#     Time: 20110 ns  Iteration: 3  Instance: /receiverfinal_vhd_vec_tst/i1/comp_sckg/comp_fpll/altpll_component/cycloneiii_altpll/m5

I checked the PLL Summary report, it say that the PLL lock range is only from 31.26 Mhz to 67.73 Mhz. I think this is the source of ModelSim Warning message.

Is there any way to extend this Cyclone III PLL Lock range? How..? :confused:

Thanks in advance,... :)

Best Regards :)

Rp

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Hi Everyone,

    I have a problem here, I have a Cyclone III project utilizing a PLL. I set the PLL to generate 192 Mhz clock from input inclk0 50 Mhz (my board has this clock source). When I simulate my design in ModelSim, everything seem ok, but ModelSim give me somekind of warning message : 

    
#  ** Note: Cyclone III PLL locked to incoming clock
#     Time: 410 ns  Iteration: 3  Instance: /receiverfinal_vhd_vec_tst/i1/comp_sckg/comp_fpll/altpll_component/cycloneiii_altpll/m5
#  Simulation passed !
#  ** Note: Cyclone III PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.
#     Time: 20110 ns  Iteration: 3  Instance: /receiverfinal_vhd_vec_tst/i1/comp_sckg/comp_fpll/altpll_component/cycloneiii_altpll/m5

    I checked the PLL Summary report, it say that the PLL lock range is only from 31.26 Mhz to 67.73 Mhz. I think this is the source of ModelSim Warning message.

    Is there any way to extend this Cyclone III PLL Lock range? How..? :confused:

    Thanks in advance,... :)

    Best Regards :)

    Rp

    --- Quote End ---

    Hi,

    the lockin range is related to your input clock. 50MHz is well inside the lockin range.

    Look into your testbench how your input clock is generated. Is it 50 MHz and when does it

    start?

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The message says "loss of input clock". You have to check, why this happens with your testbench.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks pletz and FvM,

    Here is piece code of my test bench, I have quartus generate it from *vwf file : 

    
-- RCF_in_clock
t_prcs_RCF_in_clock: PROCESS
BEGIN
	FOR i IN 1 TO 16
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	RCF_in_clock <= '0';
	WAIT FOR 10000 ps;
	RCF_in_clock <= '1';
	WAIT FOR 10000 ps;
	FOR i IN 1 TO 247
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	RCF_in_clock <= '0';
	WAIT FOR 10000 ps;
	RCF_in_clock <= '1';
	WAIT FOR 10000 ps;
	FOR i IN 1 TO 39
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	RCF_in_clock <= '0';
	WAIT FOR 10000 ps;
	RCF_in_clock <= '1';
	WAIT FOR 10000 ps;
	FOR i IN 1 TO 247
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	RCF_in_clock <= '0';
	WAIT FOR 10000 ps;
	RCF_in_clock <= '1';
	WAIT FOR 10000 ps;
	FOR i IN 1 TO 447
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
WAIT;
END PROCESS t_prcs_RCF_in_clock;

    Is there something wrong in above code?

    1 signal period of 50 Mhz clock is 20 ns, so I think the input clock signal is ok.

    when I see the waveform in ModelSim wave window, clock signal start immediately.

    So what wrong with that? I tried to configure in real cyclone FPGA, and the PLL locked signal is "high", PLL seem works fine.

    I think I can't just ignore that message.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Thanks pletz and FvM,

    Here is piece code of my test bench, I have quartus generate it from *vwf file : 

    
-- RCF_in_clock
t_prcs_RCF_in_clock: PROCESS
BEGIN
	FOR i IN 1 TO 16
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	RCF_in_clock <= '0';
	WAIT FOR 10000 ps;
	RCF_in_clock <= '1';
	WAIT FOR 10000 ps;
	FOR i IN 1 TO 247
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	RCF_in_clock <= '0';
	WAIT FOR 10000 ps;
	RCF_in_clock <= '1';
	WAIT FOR 10000 ps;
	FOR i IN 1 TO 39
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	RCF_in_clock <= '0';
	WAIT FOR 10000 ps;
	RCF_in_clock <= '1';
	WAIT FOR 10000 ps;
	FOR i IN 1 TO 247
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	RCF_in_clock <= '0';
	WAIT FOR 10000 ps;
	RCF_in_clock <= '1';
	WAIT FOR 10000 ps;
	FOR i IN 1 TO 447
	LOOP
		RCF_in_clock <= '0';
		WAIT FOR 10000 ps;
		RCF_in_clock <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
WAIT;
END PROCESS t_prcs_RCF_in_clock;

    Is there something wrong in above code?

    1 signal period of 50 Mhz clock is 20 ns, so I think the input clock signal is ok.

    when I see the waveform in ModelSim wave window, clock signal start immediately.

    So what wrong with that? I tried to configure in real cyclone FPGA, and the PLL locked signal is "high", PLL seem works fine.

    I think I can't just ignore that message.

    --- Quote End ---

    Hi,

    I'm not a VHDL expert, but it looks to me that you only generate ~ 1000 clock cycles.

    After that the clock stops. I think that is what message says. 20110 / 20 = 1005,5 clock

    cycles.

    ** Note: Cyclone III PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.

    # Time: 20110 ns Iteration: 3 Instance: /receiverfinal_vhd_vec_tst/i1/comp_sckg/comp_fpll/altpll_component/cycloneiii_altpll/m5

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks pletz,

    I intentionally made simulation stop at 20 us ( = 1000 clock cycles) at *vwf file, but it seem it don't stop in ModelSim at 20 us, this where the warning message appear.

    Thanks again, this solve my problem.

    Best Regards

    Rp.