--- Quote Start ---
Thanks pletz and FvM,
Here is piece code of my test bench, I have quartus generate it from *vwf file :
-- RCF_in_clock
t_prcs_RCF_in_clock: PROCESS
BEGIN
FOR i IN 1 TO 16
LOOP
RCF_in_clock <= '0';
WAIT FOR 10000 ps;
RCF_in_clock <= '1';
WAIT FOR 10000 ps;
END LOOP;
RCF_in_clock <= '0';
WAIT FOR 10000 ps;
RCF_in_clock <= '1';
WAIT FOR 10000 ps;
FOR i IN 1 TO 247
LOOP
RCF_in_clock <= '0';
WAIT FOR 10000 ps;
RCF_in_clock <= '1';
WAIT FOR 10000 ps;
END LOOP;
RCF_in_clock <= '0';
WAIT FOR 10000 ps;
RCF_in_clock <= '1';
WAIT FOR 10000 ps;
FOR i IN 1 TO 39
LOOP
RCF_in_clock <= '0';
WAIT FOR 10000 ps;
RCF_in_clock <= '1';
WAIT FOR 10000 ps;
END LOOP;
RCF_in_clock <= '0';
WAIT FOR 10000 ps;
RCF_in_clock <= '1';
WAIT FOR 10000 ps;
FOR i IN 1 TO 247
LOOP
RCF_in_clock <= '0';
WAIT FOR 10000 ps;
RCF_in_clock <= '1';
WAIT FOR 10000 ps;
END LOOP;
RCF_in_clock <= '0';
WAIT FOR 10000 ps;
RCF_in_clock <= '1';
WAIT FOR 10000 ps;
FOR i IN 1 TO 447
LOOP
RCF_in_clock <= '0';
WAIT FOR 10000 ps;
RCF_in_clock <= '1';
WAIT FOR 10000 ps;
END LOOP;
WAIT;
END PROCESS t_prcs_RCF_in_clock;
Is there something wrong in above code?
1 signal period of 50 Mhz clock is 20 ns, so I think the input clock signal is ok.
when I see the waveform in ModelSim wave window, clock signal start immediately.
So what wrong with that? I tried to configure in real cyclone FPGA, and the PLL locked signal is "high", PLL seem works fine.
I think I can't just ignore that message.
--- Quote End ---
Hi,
I'm not a VHDL expert, but it looks to me that you only generate ~ 1000 clock cycles.
After that the clock stops. I think that is what message says. 20110 / 20 = 1005,5 clock
cycles.
** Note: Cyclone III PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.
# Time: 20110 ns Iteration: 3 Instance: /receiverfinal_vhd_vec_tst/i1/comp_sckg/comp_fpll/altpll_component/cycloneiii_altpll/m5
Kind regards
GPK