Cyclone III PLL Lost Lock

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Hi Everyone,

I have a problem here, I have a Cyclone III project utilizing a PLL. I set the PLL to generate 192 Mhz clock from input inclk0 50 Mhz (my board has this clock source). When I simulate my design in ModelSim, everything seem ok, but ModelSim give me somekind of warning message :

#  ** Note: Cyclone III PLL locked to incoming clock
#     Time: 410 ns  Iteration: 3  Instance: /receiverfinal_vhd_vec_tst/i1/comp_sckg/comp_fpll/altpll_component/cycloneiii_altpll/m5
#  Simulation passed !
#  ** Note: Cyclone III PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame.
#     Time: 20110 ns  Iteration: 3  Instance: /receiverfinal_vhd_vec_tst/i1/comp_sckg/comp_fpll/altpll_component/cycloneiii_altpll/m5

I checked the PLL Summary report, it say that the PLL lock range is only from 31.26 Mhz to 67.73 Mhz. I think this is the source of ModelSim Warning message.

Is there any way to extend this Cyclone III PLL Lock range? How..? :confused:

Thanks in advance,... :)

Best Regards :)

Rp

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Hi,

the lockin range is related to your input clock. 50MHz is well inside the lockin range.

Look into your testbench how your input clock is generated. Is it 50 MHz and when does it

start?

Kind regards

GPK