Forum Discussion
3 Replies
- Altera_Forum
Honored Contributor
fan-out refers to a cable that comes out of your flip flop or combinational logic or in your case from your PLL. When PLL catches your input clock, the pll's "locked" pin becomes 1. this way it confirms that pll has locked onto the incoming clock.if you do not see "locked" pin, click the pll megafunction and check "locked output" check box, and click finish. now you will have "Locked" pin.
- Altera_Forum
Honored Contributor
Hi nicx82,
Just wonder if you are using the PLL locked output signal to drive any core logic? My understanding is this signal can be used to drive logic which need to wait for the PLL output to be stable. Do you encounter any compilation error when doing so? - Altera_Forum
Honored Contributor
i think fan-out is whatever your locked signal is connected to. The other end will see as fan-in.