Altera_ForumHonored Contributor18 years agoCyclone III max I/O frequency Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...Show More
Recent DiscussionsError (209014): CONF_DONE pin failed to go high in device 1.Implementation of lower data rate.eFUSE : Agilex F series and AGilex I series PCIe cardIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAEP4CGX22CF19C8N Failure Short D8 to C8