Excellent, thanks for confirming those things. I looked again at the Design Separation pdf, and I think I have a better idea now. If your secured and separated areas connect directly to IO pins, then the banks that those pins reside in should be isolated from the adjacent banks using those specified pins on the FPGA.
So LogicLock is necessary for design separation, but the bank isolation pins are needed only if IO pins are included in the separated modules.
Thanks for your help!
However, I have to hate you just a little bit. I started a diet recently, and now I REALLY want pancakes.