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Altera_Forum's avatar
Altera_Forum
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17 years ago

cyclone iii +jtag and prom interface

i am doing a project using altera cyclone iii fpga. i need to connect jtag and also the serial configuration device. i have referred the hand book available in the site. but there is a bid confuse on connections.

can i use the same jtag cable for programming the prom(serial configure device) also?.

can you help me pls?.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Is it a EPCS device? In that case you program the flash through the FPGA with the JTAG. You add a EPCS Controller Component (either with sopc builder och mega wizard) that which signals you assign to the pins of the flash (data0, dclk, sce and sdo). You can either program the flash with the Flash Programmer GUI in the NIOS 2 IDE (you don't need a nios core for that) or from the nios2 command shell.

    I hope this leads you in the right direction

    Best Regards,

    Ola Bångdahl
  • Altera_Forum's avatar
    Altera_Forum
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    The said EPCS controller is named SFL (serial flash loader).

    --- Quote Start ---

    You can either program the flash with the Flash Programmer GUI in the NIOS 2 IDE (you don't need a nios core for that) or from the nios2 command shell.

    --- Quote End ---

    For general designs (non NIOS II), the programming can be done from Quartus II programmer.
  • Altera_Forum's avatar
    Altera_Forum
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    As a note. Programming the EPCS device via the NIOS is significantly faster than programming it via the Serial Flash Loader. I mention this in case you are planning to use this as a production solution. We use the NIOS method to program the flash for our devices in production.

    As another note, Although you can program the EPCS through the FPGA using JTAG, you may want to consider adding the active serial header to your design as a backup for your first prototype. It is not uncommon for people to have JTAG problems on their first prototype. Having the active serial header gives you another method for programming the EPCS device. I had one board where the level translator on the FPGA's TDO line was installed backwards. I was able to load up the EPCS device with a simple program and verify that the FPGA was indeed working but the JTAG was not. Once you get everything working you can either remove the Active Serial header for production or just no load the connector.

    Just some thoughts.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    thanks for the reply. i will try the thing what you(Ola Bångdahl) have mentioned in your reply.