cyclone III fpga with measurement ADCs

You're ADCs are producing 2 * 48 * (14 + 1 + 1) => 1536 Mbit/s

Your SPI link's usefull bandwidth is way less than that, some 100 kbit/s..

There's no way to avoid loosing most of the samples; you simply don't have the read bandwidth to keep up.

So, waiting for the buffer to be fully read before overwriting is best. At least, you'll get coherent frames of digitized data.

Depending on your application, you may also consider moving some processing/trigger into your FPGA.

Ie, do you really need all the signal or just some parts? Can you add trigger logic so that the FPGA only stores part of the sampled data?