Cyclone III FPGA set to I/O mode

Hello Again.

well after, looking again and again to my design, i come to few conclusions i want to share.

the problem was actually not resolved by changing the configuration to weak pull up or bus-hold.. at that time it worked accidentally as i also made few changes to design as well.. but still at that time it seemed resolved, and working fine, BUT not as in past few dayz i added some more functionality to the design and the problem was back again, which was very annoying..as all my work was stopped because of this problem...

any how.. the final conclusion is important to be notice.. and which is.. that it turned out that i have some unused or un-assigned ports (debug ports, input and output) in my design (in BDF design file) which didnt give any problem in my Altera CPLD training kit, but here in FPGA that was the problem. .. i removed all those test ports, and recompile the design. so everything started to work as it should ...

now finally i can move on with my work :)...