Cyclone III FPGA set to I/O mode

yes, inside FPGA i haven't implemented anything for SDRAM, so yet there are only physical connection to SDRAM but nothing related to the core has been developed yet. and as i mention, that i explicitly give a logic-1 to these pins(physically connected to SDRAM) and then all work fine then.

i mean when there is no logic designed for SDRAM then why it is interfering with the core which is running separately form SDRAM, so the only thing i can think of could be some wrong configuration of FPGA or what???