Cyclone III FPGA set to I/O mode

Thanks a-lot for the reply,

yes i do check these options to pin assignments and they were as you suggested.

well now i have a strange outcome, but before that let me explain the real scenario i am having, in my design, the Cyclone iii is connected to the x86-platform, a SDRam and to ARM7, and for now i my IPCore is just communicating between x86 and ARM7, and nothing is configured for the SDRAM.

Now the strange thing is when i program my IPCore on fpga (with option, all unused pins set to tristate), all systems get hanged (x86 and ARM7). BUT when i explicitly give a VCC (1-logic) in quarts-II to the pin-outs of the FPGA (attached to SDRAM) every thing go to normal and my core starts to work, no system hang nothing what so ever... i couldn't understand this behaviour, i just want to make sure, is it some problem with fpga configuration or something else, that i have to force a vcc to unused pins to get my desire output !!!