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Altera_Forum
Honored Contributor
16 years agoCyclone III FPGA set to I/O mode
Hello all, well i am a bit new to Cyclone III FPGA, so, the problem i am having is a bit strange. i have made VHDL IP-core, which worked fine previously on my MAX-II CPLD, but now i wanted to r...
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- i mean do we have to specify any option to set the pin to IO mode? --- Quote End --- No. Just make the right assignments in the pin-assignment window. (assignments > pins). Make sure you see the pin list (view > all pins list) and you'll get pin name, direction, location, I/O standard and so on. There you can set the proper values. If your settings are not consistent within a bank, you'll get an error. Good luck, Ton