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Altera_Forum
Honored Contributor
16 years agoCyclone III FPGA set to I/O mode
Hello all, well i am a bit new to Cyclone III FPGA, so, the problem i am having is a bit strange. i have made VHDL IP-core, which worked fine previously on my MAX-II CPLD, but now i wanted to r...
Altera_Forum
Honored Contributor
16 years agowell on my fpga their are different banks, and now for example i am using a pin 69, has description (IO, PLL1_CLKOUTp) -- or --- pin 39 (IO,VREFB2N0) --- now does this mean that this pin is configured in IO or xxx mode???
i mean do we have to specify any option to set the pin to IO mode? P.S. i am using a cyclone iii EP3C16Q240C