Cyclone III development Kit

I'll bite-

1- How can I access to source codes of the GUI file (BoardTestSystem.exe)?

**You need to find who wrote your BoardTestSystem.exe and ask them. Your .exe sounds like a custom written app that could be anything.

2- Is it possible to capture data from FPGA to PC through USB.2 and save it by making a new windows file?

**Yes, it can be done.

3- Can I use bts_ddr2top project to develop FPGA codes and change these codes to match my plan?

**It is impossible to tell from this end. I can not tell which Cyclone III dev board you have, nor can I tell what bts_ddr2top is.

I would suggest trying to generate your own Quartus II project that will run on your dev board. Try blinking the LEDs (if you have them). This should get you started working with your project.

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1- How can I access to source codes of the GUI file (BoardTestSystem.exe)?

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You won't be able to.

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2- Is it possible to capture data from FPGA to PC through USB.2 and save it by making a new windows file?

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Yes. If you have a JTAG connector, you can implement JTAG communications per this tutorial:

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

However, JTAG is not particularly fast. If you need to transfer a lot of data, and your board has an ethernet connector, then you might be better off looking at implementing a NIOS II processor on the board with an ethernet connection to your PC. Altera provide example designs.

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3- Can I use bts_ddr2top project to develop FPGA codes and change these codes to match my plan?

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Yes. However, what I would typically do is extract the FPGA pin assignments from the provided example designs for your board, review the schematic, and create my own top-level design. Then re-implement the ddr2top design using the Quartus GUI and MegaWizard IP. To determine what was used in bts_ddr2top, open the project in Quartus and then open the MegaWizard, and make a note of the DDR2 settings.

Doing it this way provides you with the insight needed to build your own HDL code from scratch.

Cheers,

Dave

Hi Dave,

Thank you for considering my request and your suggestions are very useful. Unfortunately I don't have a JTAG programmer and don't have much time as well in addition I am not professional in Altera IP and MegaWizard developing, So could you please offer an easy solution to implement VHDL codes on the FPGA side and I would be pleased if you could give me a C++ project to capture data through USB and save it in new file.

thanks again and I look forward to hearing from you.

Cheers,

VHDL.Designer

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Unfortunately I don't have a JTAG programmer

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Are you sure? Most kits have them built into the kit, and you just need to add a USB cable. Which kit are you using?

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So could you please offer an easy solution to implement VHDL codes on the FPGA side and I would be pleased if you could give me a C++ project to capture data through USB and save it in new file.

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The example design contains information on which IP blocks you need to include in your design, and contains a JTAG server and C-coded client. You could replace the client with a C++ version easily enough.

Unfortunately you will have to gain some experience with the Altera tools and associated IP.

What is the digital data that you have to record? That must involve using the Altera tools and some HDL development. Who is providing the HDL code for that part of the project? Perhaps they can help you integrate the JTAG IP.

Cheers,

Dave