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Unfortunately I don't have a JTAG programmer
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Are you sure? Most kits have them built into the kit, and you just need to add a USB cable. Which kit are you using?
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So could you please offer an easy solution to implement VHDL codes on the FPGA side and I would be pleased if you could give me a C++ project to capture data through USB and save it in new file.
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The example design contains information on which IP blocks you need to include in your design, and contains a JTAG server and C-coded client. You could replace the client with a C++ version easily enough.
Unfortunately you will have to gain some experience with the Altera tools and associated IP.
What is the digital data that you have to record? That must involve using the Altera tools and some HDL development. Who is providing the HDL code for that part of the project? Perhaps they can help you integrate the JTAG IP.
Cheers,
Dave
Honored Contributor
