Cyclone III Critical Warning (15534) illegal output frequency must be less than 472.

The cyclone iii device datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf) - PLL Specifications on page 1-15 - specifies the maximum PLL output frequency of 472.5MHz. So, no - the tools aren't going to allow you to do what you're trying.

You can try building a PLL with the ratios you want but specify a lower input clock frequency. That way you'll keep the tools happy. You can then go on to drive the PLL at the frequency you want to achieve 500MHz. However, the max parameters in the datasheet are there for good reason. I'm not sure I'd expect your 500MHz output signal to look (at all) good or be particularly usable.

Cheers,

Alex