Cyclone III counter problem

FvM, thanks for the reply. I probed the signal, it's actually quite clean, no ringing on the edges. I am wondering if my clock is too slow for the FPGA. So are you aware if there's a minimum frequency requirement for the clock signal for Cyclone III devices? I know there's requirement for the input clock for PLLs; but here, the RxRClk from the external chip is used directly as the clock source for the counter and this clock is only running at 2.048MHz. The risetime / falltime on the scope is typically in the 10~12ns range. I can't seem to find relevant information on minimum frequency requirement from Altera's own literature.