Cyclone III configuration scheme

The USB blaster can program the FPGA itself in whatever configuration you use, as JTAG mode overtakes all the other modes. Themode to use depends on the configuration device you want to use and how it is connected. The easiest way with the Cyclone III is an enhanced configuration device (EPCS) in an active serial mode, as described page 9-13 of this document (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf).

With the Cyclone III you don't need to connect the USB blaster to the flash memory, you can program it by going through the FPGA and use a Serial Flash Loader image.

Thanks, the only differences between EPCS devices are the memory size? How should I choose the right one according to the FPGA?

The Cyclone III EP3C40 for example, in the document there is a table (9-3, in page 7) has something to do? or is there something else I have to check?

Yes, this table gives how many bits you need to hold one FPGA configuration and can be used to select the EPCS chips you can use. There is also a datasheet for the EPCS components on the Altera web site. The main difference between two chips is the memory size, but there can also be different physical sizes. Some EPCS chips are SO-8, and other ones are SO-16.

You may need more space than that on your flash device. For example if you plan to use two designs (one as a bootloader and another one as the application) then you need to double that size. If you want to store a software application or some extra data then you need space for that too.

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Oh ok, I think I understand a little more, where else could I read about configuration schemes? besides data sheets :)

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Sorry, you really do have to read the data sheets ... after a while (and a little experience) they do start to make sense :)

Here's a description of how to design your own:

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf)

For comparison, read the Altera PFL guide

http://www.altera.com/literature/ug/ug_pfl.pdf

Then look at the different options in the handbooks for the different FPGAs. The explanations are all very similar.

Cheers,

Dave

Hi, I'm confused again

If I have a Cyclone III FPGA, a EPCS configuration device, and I want to use USB Blaster to download configuration data to the FPGA, I understand than what is happen is this:

1 .The EPCS device is programed by USB Blaster

2 . EPCS device download configuration to the FPGA after each power up

Then am I using AS + JTAG ?

Is Figure 9-7 in the document http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf) what I need

Thanks for your answers, I´m trying to understand configuration schemes

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If I have a Cyclone III FPGA, a EPCS configuration device, and I want to use USB Blaster to download configuration data to the FPGA, I understand than what is happen is this:

1. The EPCS device is programed by USB Blaster

2. EPCS device download configuration to the FPGA after each power up

Then am I using AS + JTAG ?

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The EPCS devices are essentially re-branded SPI flash. To program them, you need to issue SPI sequences. There's two ways to do this using Altera's tools and a USB-Blaster;

1. AS header.

The USB-Blaster gets plugged into an AS header, which connects to the SPI pins on the EPCS flash. The USB-Blaster is then used to program the SPI flash directly. In this scheme, the FPGA just stays out of the way.

2. JTAG header.

The USB-Blaster gets plugged into a JTAG header, which connects to the JTAG pins on the FPGA. The Quartus programmer configures the FPGA with a JTAG-to-SFL (serial flash loader) bridge, and then issues JTAG commands that are converted into SPI commands. These commands can be used to read the serial flash IDs and to program the device. This is called 'indirect' programming.

I personally prefer the wiring of the latter scheme, i.e., just wire a USB-Blaster into the JTAG chain on your board, include a JTAG header on the board, and do not include an AS header.

Since you can configure the FPGA EPCS pins as user I/O after the device has configured, you can write your own SPI interface logic and software to program the flash. Eg., you can use a large Spansion device such as the S25FL512S device to program the Cyclone device on power up, and then you can use your own custom controller to access the device using the faster Quad-I/O and DDR I/O modes and 32-bit addressing modes (that are not supported by Altera's flash programming tools). The 'extra' locations in the flash can be used for reconfiguration images, configuration images for FPGAs, or boot code for a processor.

When you turn power on to your board, the Cyclone device checks its MSEL pins, and determines that it needs to configured from an external SPI flash device. The FPGA then issues SPI read (or fast read) commands to load the configuration data from flash. The address in SPI flash is nominally address 0, however, using the reconfiguration feature of the FPGA, you can select a fairly arbitrary start address for the image (24-bits, 32-bit aligned).

Cheers,

Dave

Thanks

Then, the second scheme (JTAG) is like figure 9-30 ? http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf)

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When you turn power on to your board, the Cyclone device checks its MSEL pins, and determines that it needs to configured from an external SPI flash device.

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I didn't know that

How should I connect MSEL pins? according to table 9-7 all pins to GND is ok ?

If you want to flash a configuration in the EPCS and have the FPGA load it automatically on power on, you need to configure the MSEL pins in one of the AS schemes, for example 0010 (AS with Standard POR)

If you put all the MSEL pins to ground (passive serial configuration) the JTAG interface will still work, but at power on the FPGA will wait to get a serial stream. The EPCS won't provide one by itself so the FPGA will just wait until to send it something through JTAG.