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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cyclone III configuration corrupts image

All,

We have 30 boards with a single EP3c25 wired for JTAG and AS configuration, as per the handbook. Several pairs of eyes have peered at the schematic and the boards and everything looks like it should. But, on most of the boards, configuration with USBBlaster results no errors but a corrupt FPGA image in the chip. Multiple tries will usually result in one good configuration that allows us to program the EPCS. Once that is done the boards work reliably. Except that they are still as difficult to configure through JTAG as ever.

The problem varies from board to board. Some are good, some are not so good and others are completely useless. Most of the boards are flaky to useless.

All the voltages look good.

JTAG signals look clean.

The programming software generates no errors.

CONFIG_DONE goes high even though the image is bad. (We can tell by LEDs on the board if the image took or not.)

We've made Altera and Cyclone III boards before and have not had these kinds of problems.

What could possibly be causing this?

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    As I understand it, CRC wouldn't help in this case: If the image is corrupted on download, the CRC would be computed on the corrupted image and tell you nothing.

    Remember, once the image has been saved into EPCS, we have no problem bringing the board up. It's ONLY through the JTAG that there's a problem.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    But, on most of the boards, configuration with USBBlaster results no errors but a corrupt FPGA image in the chip.

    --- Quote End ---

    Does "no error" mean, the AS image verifies correctly after programming?

    P.S.: How do you know, that the image is corrupted? It may be a case of unpredictlable design behaviour as well, e.g. due to asynchronous reset or PLL lock issues. I would activate the CRC output to decide if the image is actually corrupted.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Can you probe the INIT_DONE signal?

    Look at p56 (these are for PS/FPP, but the signals should do the same thing for JTAG configuration):

    http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf)

    Note how INIT_DONE goes low when programming starts, and then high again when done on p60. Note how there is a delay between CONF_DONE and INIT_DONE.

    I wonder if your FPGA is being left in the no-mans land between CONF_DONE going high and INIT_DONE going high.

    See p63 for enabling the INIT_DONE output.

    Cheers,

    Dave