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Altera_Forum
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14 years ago

Cyclone III configuration corrupts image

All, We have 30 boards with a single EP3c25 wired for JTAG and AS configuration, as per the handbook. Several pairs of eyes have peered at the schematic and the boards and everything looks like...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Can you probe the INIT_DONE signal?

Look at p56 (these are for PS/FPP, but the signals should do the same thing for JTAG configuration):

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf)

Note how INIT_DONE goes low when programming starts, and then high again when done on p60. Note how there is a delay between CONF_DONE and INIT_DONE.

I wonder if your FPGA is being left in the no-mans land between CONF_DONE going high and INIT_DONE going high.

See p63 for enabling the INIT_DONE output.

Cheers,

Dave