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How would I synchronize a reset?
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Reset signals from a push-button, external reset supervisor, or from the USB-Blaster interface are asynchronous signals. The reset inputs on the registers within an FPGA have a setup and hold time (called the reset recovery and removal time). If you violate this, then weird things happen.
You synchronize the external reset to each clock domain by running the signal through a reset synchronizer circuit. Altera has examples. Cliff Cummings of Sunburst design also has several good papers which discuss the topic.
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I seems to me that all that is handled by the USB Blaster.
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Nope. If you're using it to program the FPGA, that's all it does.
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Second, i had the same idea, but to use signal tap requires that I am able to configure a bad board, which is what I can't do.
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Perhaps you can program the image into the boot device and then try connecting?
Cheers,
Dave
Honored Contributor
