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I've checked. INIT_DONE toggles and goes high at the end, as it's supposed to.
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It sounds like the FPGA likes what it is receiving then.
Did you put any thought into FvM's suggestion - have you synchronized the reset to the clock domains within the FPGA? Have you checked your PLLs are locking ok?
I'd recommend putting a SignalTap II instance into the design. Then download and let Quartus communicate with the instance. If it
can communicate, then you have a design error. If Quartus cannot communicate, then there must be some form of corruption - however its a strange one, since nSTATUS would normally go low in that case.
Cheers,
Dave
Honored Contributor
