Forum Discussion
Honored ContributorCyclone III AS configuration bizarreness
I am using a cyclone III (EP3C25F324C8N) with an EPCS16 configuration device.
I am programming the configuration device through the FPGA with the serial flash loader. The problem is that the Cyclone III device will not configure itself from the EPCS16. It is stuck in an endless loop of retries UNTIL I MOMENTARILY SHORT THE nSTATUS PIN TO 3.3 VOLTS!!!! (...I discovered this by accident, no grounding the pin doesn't do it.) As soon as I do that the device configures and runs my test program (blinks LEDs). I also tried driving it high momentarily with an 8051 to no avail. Any ideas? Thanks, Rob UPDATE: It also configured when I touched CONF_DONE with a probe. Upon further investigation I found that adding a 100 pF capacitor from CONF_DONE to GND fixes this problem ...no idea why.31 Replies
Altera_ForumI tried a 25R resistor between the FPGA and EPCS on the DCLK line. This doesn't fix the problem. The FPGA is back to not configuring until I touch the pin with probe/screwdriver.
Back to the magic 100pF I suppose..... :)- Altera_Forum
Hello,
sorry for leading you in the wrong direction. 30 mm distance is effectively no distance for this kind of signals, with proper ground and supply, I can't see any reason your design may be responsible for. In this case, I think it's an Altera chip design problem related to Cyclone III or EPCS. One may be able to see it with active probes, but Altera should take care about. Best regards, Frank - Altera_Forum
I am also seeing a problem like this.
I'm using an EPCS64SI16N to configure a CycloneIII EP3C25F324C8NES (first device) and ArriaGX EP1AGX50DF780C6N (second device). The FPGAs are constantly reconfiguring. The CONF_DONE line goes high for about 350ns, then the nSTATUS transitions from high to low and the EPCS_nCS line transitions from low to high. 310ns after that the CONFIG_DONE line goes low again. Roughly 375ns after that the nCEO of the CycloneIII goes high. The nCONFIG line stays high throughout the process. A small amount of capacitance (my scope probe is 8pF, same effect with a 20pF cap) added to the CONF_DONE line will cause a successful configuration. The DCLK signal probed at the config device and ArriaGX looks good. 10K pullup resistors are on the nSTATUS, nCONFIG, and CONF_DONE lines. I'm not sure about adding a cap to the CONF_DONE line and then calling the problem fixed. Does anyone have any more ideas on this problem? Thanks. - Altera_Forum
I see that your CycloneIII is an engineering sample. So is the one I am using EP3C25E144C8NES. Perhaps this is a bug in the Cyclone III engineering samples?
- Altera_Forum
You should file an SR with the Altera MySupport line.
I seem to recall something with the ES devices and voltage levels and / or where certain signals were connected to (Vccint vs. Vccio, etc). File and SR. - Altera_Forum
Hi Folks,
I am seeing correct AS (.pof) and JTAG (.sof) configuration of my EPCS128 and EP3C16 devices respectivly. However .JIC configuration fails to fire up the system. The Altera programmer reports that all is well, but the Config-done pin is never released. I have filed an SR with Altera as I suspect the .JIC is not being generated correctly. - Altera_Forum
I've been using a Cyclone III with a EPCS128. My JTAG port works fine for debug &etc and I can program the EPCS128 OK using a separate header connected to it as per data sheet. In the latter case the Cylone subsequently configures fine from the EPCS128 at power up. However, if I program the EPCS128 via the JTAG port using a JIC file, while programming apparently completes successfully, the Cylone won't subsequently initialise. So it may be that it's something to do with the JIC file??
I'm presuming you've fitted the series resistor on the data pin of the serial memory? If not, this might explain why a bit of capacitance on the clock helps. Regards Andy - Altera_Forum
This configuration thing is highly annoying - hard to do a confident design for mass-production with tight schedules while this is unresolved. I had exactly the same situation with the probe/screwdriver on CONF_DONE & shorting nSTATUS high. When adding a large cap (>1000uF) on the 3.3V line, then that will not work anymore either. This will also be influenced by the reference used for the pullups and MSEL's, since the behaviour completely changed when I changed the reference used for MSEL from VCCA to VCCIO (3.3V). Athough the errata sheet also makes mention of this, it still didn't really help regardless of tying to VCCIO or VCCA.
- Altera_Forum
I must confess, that I didn't experience any of the said problems with Cyclone III, apart from a case, where a customer connected VCCA to 1.2V by mistake (according to the Cyclone II use). Some reports are sounding really strange, e. g. the screwdriver thing. However, the manual discusses possible problem with non-monotonous VCCA rise and unsuitable connection of configuration pins. To my opinion, the issue may occur only when supplying VCCA by a separate SMPS. When supplying VCCA with a LDO from 3.3V as we did, this can't happen.
- Altera_Forum
Could this be a problem just in Quartus 7.1. We are having a similar problem and we did find that for a small design just RTL (Cyclone III C25, Industrial samples)
Quartus 8.0 works with and without the capacitance that people is talking about with and without compress programming file Quartus 7.1 SP1 seems to work better with uncompress data streams (no idea why) and works with compress data stream when using the capacitance. With a design which includes an embedded Nios running form embedded Memories it works in 8.0 and it doesn´t in 7.1. That´s it mean that the .sof is different from the versions and it is just a matter of luck? Otherwise it something special when using Quartus 8.0 about loading from the EPCS? Could it be something depending on the streaming of the configuration file?
