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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cyclone III 3.3V LVTTL

Hello,

In my design I have a 3.3V LVTTL interface with a silab PLL which operates at 2.5V LVCMOS.

The Voh value of the lvcmos is 2.1V and the Vih of the 3.3V LVTTL is 1.7V.

Now, since the noise margin is 0.4V I guess that no problem will occur.

Should I be careful of anything else?

Is there any problem with connecting these two interfaces directly?

(direction of 3.3V to 2.5V is lowered with voltage divider).

I thank you all,

Boris.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Looks O.K. in my opinion. I would do the same. You should check, that no reflections are present, causing possible double clocking.