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Altera_Forum
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16 years ago

Cyclone III-120: M9K read, write failure

Hi, In our design I have a custom memory controller connected to the Avalon MM bus, with one Avalon MM interface, and at the other side of the controller I have four instantiations of 512x32b memo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi

I have changed the memory structure from three memory block behind on Avalon MM interface to one larger memory block. After changing the memory controller I did some tests with succes.

It works, but still can not find any good reason why the previous design didn't work correctly. As I said, I measure the same timing diagrams on three memory blocks, but one refuse to remember what I a write.

Bye

Bert