Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Cyclone III-120: M9K read, write failure

Hi, In our design I have a custom memory controller connected to the Avalon MM bus, with one Avalon MM interface, and at the other side of the controller I have four instantiations of 512x32b memo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi Pete

Yes, although the design is initially made in 8.1, I did an upgrade to 9.0SP1, so not 9.0Sp2. As far as I can see the timing analysis bug is already solved in SP1, but I will get SP2 and see what happens.

Thanks!

Bert