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Altera_Forum
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15 years ago

Cyclone III & EPCS16 configuration / DCLK signal

I have a question about the configuration of a Cyclone III with a EPCS16 in AS mode.

I have 8 prototype boards for development. JTAG program debugs OK. The POR configuration fails on 2 boards and intermittent on another 2. The solution is to place a 22pF cap on the DCLK at the EPCS device (I discovered this while using my scope probe).

I am using Standard Speed AS.

The EPCS is at 3V3, the MSEL pins are at 2V5.

It is an 8-layer board with ground and power plane, but could this be poor routing / layout problem?

The trace is 30-40 mm max.

Are there any obvious things to look out for / have others had similar?

Regards

Konrad

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I am seeing this problem now. Anyone else see this. My concern is that the ALTERA documentation says a maximum of 15pf on the DCLK pin, what can this really be?