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Altera_Forum
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13 years ago

Cyclone III -- IO port in VHDL help

I'm writing a small code to simulate the I2C.

In VHDL, the "sda_io" is defined as an IO port. I thought this simple statement should work:

sda_io <= '0' when drive_sda = '1' else (other => 'Z');

but there is an error message during compliation:

Error (10514): VHDL aggregate error at cycloneIII_3c25_start_my_first_fpga_top.vhd(101): can't determine type of aggregate -- found 0 possible types

In the previous design, I used Xilinx FPGA with Verilog HDL, these statements worked well:

IBUF sda_ibuf (.I (sda_io), .O (sda_in));

OBUFE sda_obuf (.I (1'b0), .E (drive_sda), .O (sda_io));

I have tried to find the Altera equivalent components (IBUF, OBUFE etc ...) to instantiate, does anyone know what these could be and where to find in Altera Quartus?

Thanks for helping a newbie.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    if sda_io is a std_logic, I think you meant:

    sda_io <= '0' when drive_sda = '1' else 'Z';

    first of all, the keyword is "others" not other, and you cannot use others on a non-array signal.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    It's a VHDL newbie mistake, this statement works:

    --- sda_io <= '0' when drive_sda = '1' else 'Z'; ---

    I still wish to know where and how to find the Altera's equivalent components of Xilinx's IBUF and OBUFE to instantiate in the design.

    Thanks for your help.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    the part you are looking for is the ALT_IOBUF component. you can use it in VHDL from this library:

    LIBRARY altera;

    USE altera.altera_primitives_components.all;

    quarus help will tell you more.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Check the synthesis results. Once upon a time, the recommended syntax for a tri-state was to have the 'Z' first, i.e., 

    
io <= 'Z' when (io_oe = '0') else io_out;

    But that could have been 'fixed' in newer versions of the tools.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    It's a VHDL newbie mistake, this statement works:

    --- sda_io <= '0' when drive_sda = '1' else 'Z'; ---

    I still wish to know where and how to find the Altera's equivalent components of Xilinx's IBUF and OBUFE to instantiate in the design.

    Thanks for your help.

    --- Quote End ---

    you only need to use inout for the sda_io